Post-fabrication self-aligned initialization of integrated devices

ABSTRACT

A phase change memory (PCM) cell that includes a first electrode contacting a first layer of material having a first chemical composition. The PCM cell also includes a second layer of material having a second chemical composition and a second electrode contacting the first layer of material or the second layer of material. The PCM cell is configured for receiving at least one electrical current pulse flowing from the first electrode to the second electrode to locally heat a region of the first layer and the second layer to cause at least one of inter-diffusion and liquid mixing of the first layer of material and the second layer of material, resulting in a self-aligned region of phase change material having a chemical composition that is a mixture of the first chemical composition and the second chemical composition.

DOMESTIC PRIORITY

This application is a divisional of U.S. patent application Ser. No.13/833,139, filed Mar. 15, 2013 which is a divisional of U.S. patentapplication Ser. No. 12/873,058, filed Aug. 31, 2010, now patented asU.S. Pat. No. 8,575,008 and all the benefits accruing therefrom under 35U.S.C. §119, the contents of which in their entirety are hereinincorporated by reference.

BACKGROUND

This present invention relates generally to computer memory, and morespecifically to phase change memories (PCMs).

A PCM is a form of resistive non-volatile computer random-access memory(RAM) that stores data by altering the state of the matter from whichthe device is fabricated. Phase change materials can be manipulated intotwo or more different phases or states, with each phase representing adifferent data value. Generally, each phase exhibits differentelectrical properties (or different resistance values). The amorphousand crystalline (or polycrystalline) phases are typically two phasesused for binary data storage (1's and 0's) since they have detectabledifferences in electrical resistance. Specifically, the amorphous phasehas a higher resistance than the crystalline phase.

Chalcogenides are a group of materials commonly utilized as phase changematerial. This group of materials contains a chalcogen (Periodic TableGroup 16/VIA) and another element. Selenium (Se) and tellurium (Te) arethe two most common elements in the group used to produce a chalcogenidesemiconductor when creating a PCM memory cell. Example chalcogenidesinclude Ge₂Sb₂Te₅ (germanium-antimony-tellurium or “GST”), SbTe₃, andIn₂Se₃.

Altering the phase change material's state can be achieved by heatingthe material to a melting point and then cooling the material to one ofthe possible states, or by heating an amorphous region to, or near, acrystallization temperature to convert some or all of the amorphousmaterial to crystalline form. A current passed through the phase changematerial creates heat and causes the phase change material to melt.Melting and gradually cooling down the phase change material allows timefor the phase change material to form the crystalline state. Melting andabruptly cooling the phase change material quenches the phase changematerial into the amorphous state. Heating to below the meltingtemperature can also be used to crystallize amorphous material withoutmelting.

SUMMARY

An embodiment is a method of creating a localized region of materialhaving a target chemical composition. The method includes defining anelectrical circuit on a substrate, and depositing on the electricalcircuit one or more layers of materials having one or more chemicalcompositions. An electrical current pulse is applied to the electricalcircuit to create a self-aligned localized region having the targetchemical composition. Applying the electrical current pulse causes aportion of the one or more layers of materials to be heated, resultingin the target chemical composition.

Another embodiment is a method of defining an active region of a phasechange memory (PCM) cell. The method includes depositing a first layerof material having a first chemical composition, and depositing a secondlayer of material having a second chemical composition on top of thefirst layer of material. An electrical pulse is applied to locally heata region of the first layer and the second layer to cause at least oneof an inter-diffusion and a liquid mixing of the first layer of materialand the second layer of material, resulting in a PCM cell that includesa self-aligned region made up of a phase change material that is amixture of the first chemical composition and the second chemicalcomposition.

Another embodiment is a PCM cell that includes a first electrodecontacting a first layer of material having a first chemicalcomposition, a second layer of material having a second chemicalcomposition, and a second electrode contacting the first layer ofmaterial or the second layer of material. The PCM cell is configured forreceiving at least one electrical current pulse flowing from the firstelectrode to the second electrode to locally heat a region of the firstlayer and the second layer to cause at least one of inter-diffusion andliquid mixing of the first layer of material and the second layer ofmaterial, resulting in a self-aligned region of phase change materialhaving a chemical composition that is a mixture of the first chemicalcomposition and the second chemical composition.

A further embodiment is a design structure tangibly embodied in amachine readable medium for designing, manufacturing, or testing anintegrated circuit. The design structure has a substantially planarsurface and includes a PCM cell. The PCM cell includes a first electrodecontacting a first layer of material having a first chemicalcomposition, a second layer of material having a second chemicalcomposition, and a second electrode contacting the first layer ofmaterial or the second layer of material. The PCM cell is configured forreceiving at least one electrical current pulse flowing from the firstelectrode to the second electrode to locally heat a region of the firstlayer and the second layer to cause at least one of inter-diffusion andliquid mixing of the first layer of material and the second layer ofmaterial, resulting in a self-aligned region of phase change materialhaving a chemical composition that is a mixture of the first chemicalcomposition and the second chemical composition.

Additional features and advantages are realized through the techniquesof the present embodiment. Other embodiments and aspects are describedherein and are considered a part of the claimed invention. For a betterunderstanding of the invention with the advantages and features, referto the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter that is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 illustrates a system programming a phase change memory (PCM)device in accordance with exemplary embodiments of the presentinvention;

FIG. 2 depicts an example structure of a memory array in accordance withexemplary embodiments;

FIGS. 3A-3B depict vertical path memory cell structures in accordancewith embodiments described herein;

FIGS. 4A-4D depict parallel path memory cell structures in accordancewith embodiments described herein;

FIG. 5 depicts several side views of an embodiment of a self-alignedparallel cell with a threshold switching layer;

FIG. 6 depicts a parallel cell after a small reset pulse has beenapplied to create an amorphous region inside a crystalline region;

FIG. 7 depicts a process flow for creating and initializing a phasechange memory in accordance with an embodiment;

FIG. 8 depicts several side views of an embodiment of a self-alignedparallel cell with several intermixed threshold switching layers andcomplementary layers;

FIG. 9 depicts several side views of an embodiment of a self-alignedparallel cell with a phase change material layer and an insulator layer;

FIG. 10 depicts several side views of an embodiment of a self-alignedmushroom cell with multiple threshold switching material layers andcomplementary material layers;

FIG. 11 depicts several side views of an embodiment of a self-alignedmushroom cell with two layer of phase changing material enclosing a thinlayer of sacrificial insulator material;

FIG. 12 depicts several side views of an embodiment where a resist layerhas been deposited on a parallel path PCM cell;

FIG. 13 depicts several side views of an embodiment where a heatgenerating structure is sacrificial and removed by etching; and

FIG. 14 is a flow diagram of a design process used in semiconductordesign, manufacture, and/or test.

DETAILED DESCRIPTION

A phase change memory (PCM) requires a relatively significant effectivepower density (e.g., W/nm³ or “watts per molten cubic nanometer”) tooperate the PCM cell into a reset state. Operating the PCM cell into areset state includes creating a substantial quantity of amorphousmaterial so to significantly increase the cell resistance over thepolycrystalline (or set) state resistance. This requires the use ofrelatively large access devices that are capable of driving the currentsrequired for resetting the cells and sustaining the voltages required toinduce threshold switching in the amorphous phase.

The large power requirement has lead to research in the area of theminiaturization of the PCM cell and its components (e.g., theelectrodes). In particular, in vertical cell structures such as themushroom cell or the uTrench cell, the bottom electrode is typicallyobtained using sub-lithographic methods, in order to reduce as much aspossible the active region of the device (i.e., the spatial region inwhich the electrical conduction and the thermal phenomena happen).

An embodiment of the present invention provides for the definition of aself-aligned sub-lithographic active region. The definition of theactive region is carried out after fabrication (or even after packaging)and relies on a chemical reaction that is triggered by extreme heatingin the hottest region between two electrodes. Benefits to this approachare that the active portion (i.e., the phase changing portion) of thephase change material will be confined in a small region, thus allowinglow power operation. Benefits also include the ability to reduce themask count and the precision required in phase change materialpatterning (also allowing several cells to share the same patch of phasechange material).

In accordance with embodiments described herein, two or more layers ofmaterial having different compositions are deposited, and then one ormore electrical heating pulses are utilized to cause the diffusionand/or mixing of the two material layers. The result is a region ofmaterial having a composition that is a combination of the two layers.This approach is used to create a sub-lithographic PCM region in thehigh-field region (i.e., the region where current crowding is maximum)near two electrodes of a memory device. In one embodiment, the firstlayer over (or between) the two electrodes is what is often referred toas an ovonic threshold switch (OTS) amorphous material that breaks downand conducts electricity when the electric field (or temperature)exceeds some threshold. The second layer contains donor material (eitherdifferent elements or different ratios of the same elements) that, whenmixed with the OTS layer, creates a PCM material that can exist in botha high resistance amorphous state and low resistance quasi-crystallinestate.

As used herein the term “conducting material” refers to any materialthat conducts electricity (implemented, for example by an electrode).The conductive material may be composed of, but is not limited to one ormore of: titanium, tungsten, titanium nitride, and titanium aluminumnitride. Optionally, a non-metallic conductive material can be used,such as, but not limited to polysilicon or other semiconductor or dopedsemiconductor material.

As used herein the term “insulator” or “insulator material” refers toany material that resists the flow of electric current. Examples ofinsulator materials include, but are not limited to: silicon dioxide,aluminum oxide, silicon nitride, and titanium oxide. Insulators may alsobe referred to as dielectrics.

As used herein, the term “phase change material” refers to any materialthat can be manipulated into two or more different phases or states,such as, but not limited to the chalcogenides described above. Fordiscussion purposes, GST is used below as an example of a phase changematerial. This is not intended to limit embodiments to GST as otherembodiments may utilize other phase change materials.

As used herein, the term “phase change material (crystalline)” refers tophase change material that is in a crystalline or polycrystalline phase.

As used herein, the term “phase change material (amorphous)” refers tophase change material that is in an amorphous phase. The amorphous phasehas a higher resistance value than the crystalline phase.

As used herein, the term “threshold switching material” refers to anymaterial that in normal conditions has minimal conductivity and thatbreaks down and conducts electricity when the electric field (ortemperature) exceeds some threshold. The OTS amorphous materialdescribed above is an example of a threshold switching material. In anembodiment, the amorphous threshold switching material exhibits highelectrical resistivity at low electric field strength and substantiallyreduced electrical resistivity at electric field strengths above athreshold.

As used herein, the term “complementary material” refers to any donormaterial (either different elements or different ratios of the sameelements as the threshold switching material) that, when mixed with thethreshold switching material, creates a PCM material that can exist inboth a high resistance amorphous state and low resistancequasi-crystalline state.

As used herein, the term “self-aligned” refers to a geometric region theposition of which is defined by the shape and position of somepreviously defined regions. For example, the temperature isocurve for aspecific temperature in a PCM cell driven with a given electrical signalis “self aligned” to the so-called active region of the PCM cell, i.e.,the region that comprises most of the current flow and wheretransformation between amorphous and polycrystalline material happens.

As used herein, the term “diffusion” refers to molecules of a firstmaterial entering the bulk of an adjacent second material, usually witha speed that increases with the temperature of the two materials

As used herein, the term “liquid mixing” refers to the formation of athird material by liquid phase mixing of two starting materials

In one embodiment, where a target chemical composition is that of aphase change material (such as GST), the threshold alloy, or thresholdswitching material, is Ge_(x)Sb_(y)Te_(z); and the complementary alloy,or complementary material, is Ge_(1-x)Sb_(2-y)Te_(4-z). In thisembodiment, for every mole of the threshold alloy that is deposited, twomoles of the complementary alloy are deposited. The layers of thethreshold alloy and the complementary alloy can be arranged in differentindividual thicknesses and number of layers, and only the totalstoichiometric quantity has to be respected.

Reduction of the programming power is important in PCM technologybecause it has an impact on the design of the circuitry required toprogram the memory cell. In an exemplary embodiment, the circuitryrequired to program the memory cell includes: (i) an access device(e.g., a diode or a transistor); (ii) a bit line to support theprogramming current; (iii) peripheral circuitry that drives the bitline; and (iv) charge pumps whenever present.

FIG. 1 illustrates a system for programming a PCM in accordance withembodiments. The system depicted in FIG. 1 includes a processor 102, anda memory array 108. The processor 102 depicted in FIG. 1 includes acontroller 104 and an address decoder 106. As depicted in FIG. 1, thememory array 108 includes a plurality of memory cells 110. In anembodiment, a memory cell 110 is configured to store binary datarepresented by at least two resistance states or configurations of phasechange material (referred to as a “single level cell” or “SLC”). One ofthe resistance states is a high resistance state. In another embodiment,the memory cell 110 is configured to store more than two valuesrepresented by three or more resistance state ranges or configurationsof phase change material (referred to as a “multiple level cell” or“MLC”).

In an embodiment, the controller 104 identifies and selects memory cells110 in the memory array 108 for programming. The address decoder 106then decodes memory addresses from the controller 104 and applies arange of word line biases to the memory cells 110 in the memory array108.

FIG. 2 depicts an example structure of a memory array in accordance withan embodiment. As shown in FIG. 2, the memory array includes a pluralityof memory cells 202 electrically coupled to bit lines 204 and word lines206. In an embodiment, each memory cell 202 is comprised of a memoryelement access device and a resistive memory element for storing aresistance value. In an embodiment, the resistive memory element is aPCM element that includes phase change material and two electrodes. Inan embodiment, the data in a memory cell 202 connected to a bit line 204is accessed (read or programmed) by turning off the access devices ofother memory cells 202 connected to the bit line 204. The access devicesof the other memory cells 202 are turned on and off using the word lines206.

FIGS. 3A-3B depict vertical path memory cell structures in accordancewith embodiments described herein. FIG. 3A depicts a series-path memorycell 302, also known as “pore cell” that includes a bottom electrode304, a dielectric layer 306, phase change material 308, and a topelectrode 314. The phase change material 308 shown may be comprised ofcrystalline or polycrystalline phase change material 310 and a volume ofamorphous phase change material 312. For many moderate to high cellresistance levels, the amorphous phase change material 312 almostcompletely occludes the cross-section of the phase-change material,forcing a significant fraction of the current to flow through theamorphous phase change material 312 and crystalline phase changematerial 310 regions in series. FIG. 3B depicts a side view of a memorycell 316, also known as “mushroom” cell, where the bottom electrode 304is sub-lithographic and the phase change material (e.g., GST) patterningis not sub-lithographic.

FIGS. 4A-4D depict parallel path memory cell structures in accordancewith embodiments described herein. U.S. patent application Ser. No.12/823,924 filed Jun. 25, 2010 describes parallel path memory cellstructures and is hereby incorporated by reference in its entirety.FIGS. 4A-4D depict a top view, looking down through a storage materiallayer. The exemplary structures in FIGS. 4A and 4B are characterized byone sub-lithographic strip electrode (the first conductive electroderegion 404) (e.g., a plated trench wall having a plating thickness ofabout five nanometers) orthogonal to another electrode (the secondconductive electrode region 406) (e.g., a plated trench wall or a solidmetal line) with a sub-lithographic inter-electrode gap defined by athickness of a deposited insulator film or layer (the insulator layer408) (e.g., having a thickness of about three to twenty nanometers, orup to the feature size for the adopted lithography). Both FIGS. 4A and4B depict an in-plane dual-electrode structure (i.e., both electrodesare on the bottom of the GST layer and the top surface of the GST isinsulated). In an embodiment, both electrodes and the GST thickness aresub-lithographic and the GST patterning is not sub-lithographic.

Turning now to FIG. 4C, in an exemplary embodiment, at least a portionof the first conductive electrode region 404 and the second conductiveelectrode region 406 are covered with a layer of storage material. In anexemplary embodiment, the exemplary cell structure provides a small meltregion 410 that grows asymmetrically, obscuring a variable percentage ofat least the first conductive electrode region 404 as the currentincreases.

Turning now to the embodiment in FIG. 4D, the first conductive electroderegion 404 and the second conductive electrode region 406 a are notorthogonal to one another. In this embodiment, the current distributionand the melt region will no longer be symmetric with respect to the axisof the first conductive electrode region 404. In fact, this embodimenthas no planes of symmetry.

FIG. 5 depicts several side views of an embodiment of a self-alignedparallel cell with a threshold switching layer. Parallel cell 502includes two electrodes separated by an insulator, and topped with athreshold switching material located under a complementary material. Inan embodiment, the threshold switching material exhibits high resistancewhich results in a reduced cell-to-cell electrical interference and theability for more than one cell to share the same GST patch. Parallelcell 504 depicts a current path 510 (or current flow passing through, inthis example, the threshold switching material) when a reset pulse isapplied to the conducting material (e.g., an electrode) on the rightside of the parallel cell 504. As shown in the parallel cell 504, thethreshold switching material and complementary material are heated thusmelting a region 508 when the first reset pulse is applied. Parallelcell 506 depicts the result of the heating of the threshold switchingmaterial and the complementary material by the first reset pulse. Asshown in parallel cell 506, the first reset pulse mixes the two layers(threshold switching material and complementary material) creating aself-aligned region of phase change material having a target chemicalcomposition. In an embodiment, the target chemical compositionapproximates GST (a phase change material) in a crystalline state. In anembodiment the crystalline state in region 508 is obtained by slowlyreducing trailing current in the first reset pulse.

FIG. 6 depicts a parallel cell 602 after a small reset pulse has beenapplied to create an amorphous region inside the crystalline regiondepicted in parallel cell 506.

The creation of the GST in a crystalline state is an initializationprocess that is generally performed after manufacturing (or afterfabrication) and before the cell is used to store data. In addition, theinitialization process may be performed periodically during the lifetimeof the memory device.

FIG. 7 depicts a flow of a process for creating and initializing aself-aligned PCM cell in accordance with an embodiment. At block 702, afirst layer of a first material is deposited (e.g., a thresholdswitching material). At block 704, a second layer of a second materialis deposited (e.g., a complementary material). At block 706, aself-aligned region of phase change material is created. In anembodiment, the self-aligned active region is created as described abovein FIG. 5 by applying a reset pulse that mixes a threshold switchingmaterial and a complementary material. Other manners of creating theself-aligned active region are described below. In an embodiment, thephase change material that is created is a crystalline phase changematerial region and block 708 is skipped. In another embodiment, atblock 708, a crystalline phase change material region is created in thephase change material by applying a relatively large set electricalpulse, via the electrodes, to the phase change material. After thecrystalline phase change material region is created, the cell is nowinitialized and ready for use in storing data. At block 710, data isstored in the memory cell by creating a second, smaller amorphousmaterial region inside the active crystalline material region using areset pulse that is smaller than the set pulse applied in block 710.

Blocks 704-710 of the process described in FIG. 7 may be performed bythe manufacturer after fabrication, by a customer prior to using thememory device and/or periodically as part of a maintenance procedure.

In an embodiment, the size of the active crystalline region iscontrolled (e.g., via the set pulse) to create a desired minimum cellresistance, which is the result of the parallel combination of an outerpath through any crystalline material outside of the amorphous regionplus an inner path through the active crystalline region. Controlling(e.g., being able to adjust or adjusting) the size of the activecrystalline region provides precise control of the minimum cellresistance and enables data storage through the creation of a fixed orvariable-sized amorphous region inside of the active crystalline region.In an embodiment, the volume of the amorphous phase change material isincreased by applying an electrical pulse having an amplitude largerthan a previously applied electrical pulse and/or a duration shorterthan a previously applied electrical pulse, the applying via one or bothof the electrodes. In an embodiment, the volume of the amorphous phasechange material is decreased by applying an electrical pulse having anamplitude lower than a previously applied electrical pulse and/or aduration longer than a previously applied electrical pulse.

In embodiments, normal operation of the cell includes the steps ofcreating an amorphous or a crystalline region by melting a region andthen rapidly quenching (to create amorphous material) or reducing thecurrent so that the region crystallizes while cooling (to createcrystalline material). Another typical operation is to convert some orall of an amorphous region without melting, by heating enough, and forlong enough time, for crystallization to occur. In embodiments, thememory cell is programmed to a specific resistance value by applying anelectrical signal large enough to cause the melting of a region thatwill create an amount of amorphous material sufficient for creating thedesired resistance value. The peak value of the electrical signal can beestimated using finite element analysis of the cell. Alternatively, thecell can be programmed with a pulse that melts a sufficiently largeregion, slowly decreases to the above described peak value and isabruptly removed to quench the molten phase-change material. Inembodiments, the modes of operation of the cell are preceded by aninitialization process that confines the crystalline region into asub-lithographic area.

A process similar to the process depicted in FIG. 7 may be utilized tocreate a localized region of material on a substrate, where thelocalized region of material has a target chemical composition. In thisprocess, an electrical circuit is defined on the substrate, and one ormore layers of materials having one or more chemical compositions aredeposited on the electrical circuit. An electrical current pulse is thenapplied to the electrical circuit to create a self-aligned localizedregion that approximates the target chemical composition. Applying theelectrical current pulse causes at least a portion of the depositedlayers to be heated, and the heating causes the creation of thelocalized region of material with the target chemical composition. Anelectrical circuit can be defined or created on a substrate by means oflithographic or photo-lithographic techniques. As used herein, the term“substrate” refers to any structure on which another structure is thenbuilt. A substrate may be an insulating substrate such as, but notlimited to silica or alumina. In another embodiment the substrate is asemiconductor substrate such as a monocrystal substrate of materialsincluding, but not limited to, silicon, gallium-arsenide or germanium.Other options for a substrate include a wafer that has been previouslyprocessed with planar lithographic techniques. In an embodiment, theelectrical circuit is implemented by a network of conductive material orby a standard integrated circuit using, in addition to lithographicallydefined connections, integrated semiconductor devices such astransistors and diodes. Those skilled in the art will recognize thatembodiments of the present invention are not limited by the quality orthe purpose of the substrate and that the specific definition of acircuit defined on a substrate does not limit the applicability ofembodiments of the present invention.

FIG. 8 depicts several side views of an embodiment of a self-alignedparallel cell with several intermixed threshold switching layers andcomplementary layers. Parallel cell 802 includes two electrodesseparated by an insulator, and topped with several intermixed layers ofthreshold switching material and complementary material. Using severalintermixed layers of threshold switching material and complementarymaterial can aid in mixing the two types of material together to formthe phase change material. FIG. 8 depicts a current path 810 (or currentflow) when a reset pulse is applied to the conducting material (e.g., anelectrode) on the right side of the parallel cell 804. As shown in theparallel cell 804, the threshold switching material and complementarymaterial are heated creating a molten region when the first reset pulseis applied. Parallel cell 806 depicts the result of the heating of thethreshold switching material and the complementary material by the firstreset pulse. As shown in parallel cell 806, the first reset pulse mixesthe two layers (threshold switching material and complementary material)creating a self-aligned region of phase change material.

FIG. 9 depicts several side views of an embodiment of a self-alignedparallel cell with a phase change material layer and an insulator layer.Parallel cell 902 includes two electrodes separated by an insulator, andtopped with a thin insulator layer located under a phase changematerial. Parallel cell 902 depicts a current path 910 (or current flow)when a reset pulse is applied to the conducting material (e.g., anelectrode) on the right side of the parallel cell 904. As shown in theparallel cell 904, the insulator and phase change material are heatedcreating a molten region 908 when the first reset pulse is applied.Parallel cell 906 depicts the result of the heating of the insulator andthe phase change material by the first reset pulse. As shown in parallelcell 906, the first reset pulse locally degrades the insulator layer andthe phase change material (e.g., the GST) directly contacts theelectrodes creating a self-aligned active region.

FIG. 10 depicts several side views of an embodiment of a self-alignedmushroom cell with multiple threshold switching material layers andcomplementary material layers. Mushroom cell 1002 includes twoelectrodes separated by the layers of threshold switching material andcomplementary material. Mushroom cell 1004 depicts a current path 1010(or current flow) when a reset pulse is applied to the conductingmaterial (e.g., an electrode) on the bottom of the mushroom cell 1004.As shown in the mushroom cell 1004, the threshold switching material andcomplementary material are heated creating a molten region1008 when thefirst reset pulse is applied. Mushroom cell 1006 depicts the result ofthe heating of the threshold switching material and the complementarymaterial by the first reset pulse. As shown in mushroom cell 1006, thefirst reset pulse mixes the layers (threshold switching material andcomplementary material) creating a self-aligned region of phase changematerial. In an embodiment, the phase change material is GST in apolycrystalline state.

FIG. 11 depicts several side views of an embodiment of a self-alignedmushroom cell with multiple threshold switching material layers andcomplementary material layers. Mushroom cell 1102 includes twoelectrodes separated by the layers of an insulating material and a phasechange material. Mushroom cell 1104 depicts a current path 1110 (orcurrent flow) when a reset pulse is applied to the conducting material(e.g., an electrode) on the bottom of the mushroom cell 1104. As shownin the mushroom cell 1104, the insulator and phase change material areheated 1108 when the first reset pulse is applied. Mushroom cell 1106depicts the result of the heating of the insulator and the phase changematerial by the first reset pulse. As shown in mushroom cell 1106, thefirst reset pulse breaks a hole through the insulator creating aself-aligned region of phase change material. The final structure can beseen as a self-aligned pore cell.

FIG. 12 depicts several side views of an embodiment where a resist layerhas been deposited on a parallel path PCM cell. On a parallel path PCMcell 1202, deposition of a GST layer 1212 has been followed by thedeposition of a thin insulating layer 1210. On top of the insulatinglayer 1210, a topmost layer of resist 1208 has been deposited. Byapplying power to the PCM cell 1202 at fabrication time, PCM cell 1204is obtained, where the active area 1214 is heated and a portion 1216 ofthe resist 1208 is sensitized. A subsequent process step is used toobtain the sensitized resist as shown in PCM cell 1206. In thisembodiment, the target chemical composition is that of the sensitizedresist 1218. As shown in PCM cell 1206 a self-aligned patterning ofsensitized resist 1218 is created which covers the active area of thephase change material. In an embodiment, a subsequent step includesetching the insulating layer 1210 and the GST layer 1212 not covered bythe sensitized resist 1218. In an embodiment, the insulator layer 1212is omitted or substituted with other materials providing heat transferand electrical properties, as well as chemical properties compatiblewith the process, the materials used in the lower layers and therequirements on the shape of the sensitized region. Positive or negativeresist can be used leading to different shapes of the developed area. Inan embodiment, an extent of the localized region is responsive to thegeometry of the electrical circuit where the PCM cell 1206 is locatedand to one or more of a magnitude (or strength) and a duration of theelectrical current pulse used to heat the portion 126 of the resist1208. In an embodiment, the self-aligned localized region defines aregion for sensitizing the chemical resist, the sensitizing occurring inresponse to the increase of temperature.

FIG. 13 depicts several side views of an embodiment where a heatgenerating structure is sacrificial and removed by etching. Thesacrificial heat generating structure 1302 shown in FIG. 13 includes aninsulator layer 1314, and sacrificial electrodes 1312 built on asubstrate 1316. As shown in FIG. 13, a high resistivity material layer1310 is deposited followed by the deposition of a resist 1308 in thetopmost layer. By applying power to the structure 1302, structure 1304is obtained, where the active area 1318 defined by the electrodes 1312is heated 1318 and a portion 1320 of the resist 1308 in the topmostlayer is sensitized. A subsequent process step resulting in structure1306 develops the sensitized resist 1322, and performs etching of theportion of the layers not covered by the developed resist, including thecircuit used to generate heat, thus creating a self aligned patterndefined by the shape of the sacrificial circuit. In an embodiment, thecircuit is only partially removed. In exemplary embodiments positive ornegative resist can be used.

Technical effects and benefits include the ability to confine the activeportion of phase change material to a very small region of a memorydevice, thus allowing ultra low power operation. Embodiments asdescribed herein allow the mask count to be reduced, allow a reductionin the precision required in phase change memory patterning, and allowseveral cells to share the same phase change memory patch.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

The method as described above is used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

FIG. 14 shows a block diagram of an exemplary design flow 1400 used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture. Design flow 1400 includes processes, machines and/ormechanisms for processing design structures or devices to generatelogically or otherwise functionally equivalent representations of thedesign structures and/or devices described above and shown in FIGS. 1-2,3A-3B, 4A-4D, 5-6, and 8-13.

The design structures processed and/or generated by design flow 1400 maybe encoded on machine-readable transmission or storage media to includedata and/or instructions that when executed or otherwise processed on adata processing system generate a logically, structurally, mechanically,or otherwise functionally equivalent representation of hardwarecomponents, circuits, devices, or systems. Machines include, but are notlimited to, any machine used in an IC design process, such as designing,manufacturing, or simulating a circuit, component, device, or system.For example, machines may include: lithography machines, machines and/orequipment for generating masks (e.g. e-beam writers), computers orequipment for simulating design structures, any apparatus used in themanufacturing or test process, or any machines for programmingfunctionally equivalent representations of the design structures intoany medium (e.g. a machine for programming a programmable gate array).

Design flow 1400 may vary depending on the type of representation beingdesigned. For example, a design flow 1400 for building an applicationspecific IC (ASIC) may differ from a design flow 1400 for designing astandard component or from a design flow 1400 for instantiating thedesign into a programmable array, for example a programmable gate array(PGA) or a field programmable gate array (FPGA) offered by Altera® Inc.or Xilinx® Inc.

FIG. 14 illustrates multiple such design structures including an inputdesign structure 1420 that is preferably processed by a design process1410. Design structure 1420 may be a logical simulation design structuregenerated and processed by design process 1410 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 1420 may also or alternatively comprise data and/or programinstructions that when processed by design process 1410, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 1420 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer. When encoded on a machine-readable datatransmission, gate array, or storage medium, design structure 1420 maybe accessed and processed by one or more hardware and/or softwaremodules within design process 1410 to simulate or otherwise functionallyrepresent an electronic component, circuit, electronic or logic module,apparatus, device, or system such as those shown in FIGS. 1-2, 3A-3B,4A-4D, 5-6, and 8-13. As such, design structure 1420 may comprise filesor other data structures including human and/or machine-readable sourcecode, compiled structures, and computer-executable code structures thatwhen processed by a design or simulation data processing system,functionally simulate or otherwise represent circuits or other levels ofhardware logic design. Such data structures may includehardware-description language (HDL) design entities or other datastructures conforming to and/or compatible with lower-level HDL designlanguages such as Verilog and VHDL, and/or higher level design languagessuch as C or C++.

Design process 1410 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures shown in FIGS. 1-2, 3A-3B, 4A-4D, 5-6, and8-13 to generate a netlist 1480 which may contain design structures suchas design structure 1420. Netlist 1480 may comprise, for example,compiled or otherwise processed data structures representing a list ofwires, discrete components, logic gates, control circuits, I/O devices,models, etc. that describes the connections to other elements andcircuits in an integrated circuit design. Netlist 1480 may besynthesized using an iterative process in which netlist 1480 isresynthesized one or more times depending on design specifications andparameters for the device. As with other design structure typesdescribed herein, netlist 1480 may be recorded on a machine-readabledata storage medium or programmed into a programmable gate array. Themedium may be a non-volatile storage medium such as a magnetic oroptical disk drive, a programmable gate array, a compact flash, or otherflash memory. Additionally, or in the alternative, the medium may be asystem or cache memory, buffer space, or electrically or opticallyconductive devices and materials on which data packets may betransmitted and intermediately stored via the Internet, or othernetworking suitable means.

Design process 1410 may include hardware and software modules forprocessing a variety of input data structure types including netlist1480. Such data structure types may reside, for example, within libraryelements 1430 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 100 nm, etc.). The data structure types may further includedesign specifications 1440, characterization data 1450, verificationdata 1460, design rules 1470, and test data files 1485 which may includeinput test patterns, output test results, and other testing information.Design process 1410 may further include, for example, standardmechanical design processes such as stress analysis, thermal analysis,mechanical event simulation, process simulation for operations such ascasting, molding, and die press forming, etc. One of ordinary skill inthe art of mechanical design can appreciate the extent of possiblemechanical design tools and applications used in design process 1410without deviating from the scope and spirit of the invention. Designprocess 1410 may also include modules for performing standard circuitdesign processes such as timing analysis, verification, design rulechecking, place and route operations, etc.

Design process 1410 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 1420 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 1490.Design structure 1490 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g. information stored in a IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures). Similar to designstructure 1420, design structure 1490 preferably comprises one or morefiles, data structures, or other computer-encoded data or instructionsthat reside on transmission or data storage media and that whenprocessed by an ECAD system generate a logically or otherwisefunctionally equivalent for one or more of the embodiments of theinvention shown in FIGS. 1-2, 3A-3B, 4A-4D, 5-6, and 8-13. In oneembodiment, design structure 1490 may comprise a compiled, executableHDL simulation model that functionally simulates the devices shown inFIGS. 1-2, 3A-3B, 4A-4D, 5-6, and 8-13.

Design structure 1490 may also employ a data format used for theexchange of layout data of integrated circuits and/or symbolic dataformat (e.g. information stored in a GDSII (GDS2), GL1, OASIS, mapfiles, or any other suitable format for storing such design datastructures). Design structure 1490 may comprise information such as, forexample, symbolic data, map files, test data files, design contentfiles, manufacturing data, layout parameters, wires, levels of metal,vias, shapes, data for routing through the manufacturing line, and anyother data required by a manufacturer or other designer/developer toproduce a device or structure as described above and shown in FIGS. 1-2,3A-3B, 4A-4D, 5-6, and 8-13. Design structure 1490 may then proceed to astage 1495 where, for example, design structure 1490: proceeds totape-out, is released to manufacturing, is released to a mask house, issent to another design house, is sent back to the customer, etc.

Aspects of the present invention are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

What is claimed is:
 1. A phase change memory (PCM) cell comprising: afirst electrode contacting a first layer of material having a firstchemical composition; a second layer of material having a secondchemical composition; and a second electrode contacting the first layerof material or the second layer of material; the PCM cell configured forreceiving at least one electrical current pulse flowing from the firstelectrode to the second electrode to locally heat a region of the firstlayer and the second layer to cause at least one of inter-diffusion andliquid mixing of the first layer of material and the second layer ofmaterial, resulting in a self-aligned region of phase change materialhaving a chemical composition that is a mixture of the first chemicalcomposition and the second chemical composition.
 2. The PCM cell ofclaim 1, wherein the first layer of material is an amorphous thresholdswitching material having high electrical resistivity at low electricfield strength and substantially reduced electrical resistivity atelectric field strengths above a threshold.
 3. The PCM cell of claim 1,wherein the first layer of material is an insulator and the second layerof material is the phase change material, or the first layer of materialis the phase change material and the second layer of material is aninsulator.
 4. The PCM cell of claim 1, wherein the PCM cell ischaracterized by a parallel path memory cell structure.
 5. The PCM cellof claim 1, wherein the PCM cell is characterized by a vertical pathmemory cell structure.
 6. A design structure tangibly embodied in amachine readable medium for designing, manufacturing, or testing anintegrated circuit, the design structure having a substantially planarsurface, the design structure comprising: a phase change memory (PCM)cell comprising: a first electrode contacting a first layer of materialhaving a first chemical composition; a second layer of material having asecond chemical composition; and a second electrode contacting the firstlayer of material or the second layer of material; the PCM cellconfigured for receiving at least one electrical current pulse flowingfrom the first electrode to the second electrode to locally heat aregion of the first layer and the second layer to cause at least one ofinter-diffusion and liquid mixing of the first layer of material and thesecond layer of material, resulting in a self-aligned region of phasechange material having a chemical composition that is a mixture of thefirst chemical composition and the second chemical composition.
 7. Thedesign structure of claim 6, wherein the PCM cell is characterized byone of a parallel path memory cell structure and a vertical path memorycell structure.